MwT-LP7 Ultra - Low Phase Noise device up to 31 GHz

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MwT- LP7

Ultra - Low Phase Noise device up to 31 GHz

All Dimensions in Microns
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CHIP THICKNESS = 125 ľm

Features:

Ultra-Low Phase Noise for Oscillator Applications up to 31 GHz

+20 dBm Output Power at 12 GHz

Also Excellent for Broadband Gain and Medium Power Applications

0.3 Micron Refractory Metal/Gold Gate

250 Micron Gate Width

Choice of Chip and Two Package Types

Download MwT-LP7 SPARAM Files (Zipped)

The MwT-LP7 is a low phase noise GaAs MESFET device with nominal quarter-micron gate length and 250-micron gate width. With deep
understanding on the physical origins of phase noise, the device is built by using a unique proprietary technology to minimize the phase
noise. This device is particularly attractive to oscillator applications requiring ultra-low phase noise up to 31 GHz or amplifiers requiring
low residue noise in the 500 MHz to 26 GHz frequency range. A 17.5 GHz DRO using this device achieved phase noise power
density as low as-119 dBc/Hz at 100 kHz off set with ample output power of +15dBm. The is also effective for either wideband
(e.g. 6 to 18 Ghz) or narrow-band applications. The chip is produced using MwT's reliable metal system and all devices are screened to
insure reliability. All chips are passivated using MwT's patented "Diamond-LikeCarbon" process for increased durability. Designers can
use MwT's unique BIN selection feature to choose devices from narrow Idss ranges, insuring consistent circuit operation.
17.5 GHz DRO Application Notes
10.0 GHz FRDRO Application Notes

DC Specifications at Ta= 25°C

SYMBOL	PARAMETERS & CONDITIONS	UNITS	MIN	TYP	MAX
IDSS	Saturated Drain Current Vds=4.0 V Vgs=0.0 V	mA	38		98
Gm	Transconductance Vds=3.0 V Vgs=0.0 V	mS	36	45
Vp	Pinch-off Voltage Vds=3.0 V Ids=1.0 mA	V		-1.5	-4.5
BVGSO	Gate-to-Source Breakdown Volt. Igs= -0.4 mA	V	-5.0	-8.0
BVGDO	Gate-to-Drain Breakdown Volt. Igd= -0.4 mA	V	-6.0	-8.0
Rth	Thermal MwT-LP7 Chip Resistance MwT-LP770, LP773	°C/W		180 380*

* Overall Rth depends on case mounting

RF Specifications at Ta= 25°C


SYMBOL	PARAMETERS & CONDITIONS	FREQ	UNITS	MIN	TYP
P1dB	Output Power at 1dB Compression Vds=5.0 V Idss=0.6 IDS=35 mA	12 GHz	dBm	18.0	20.0
SSG	Small Signal Gain Vds=5.0 V Idss=0.6 IDS=35 mA	12 GHz	dB	10.0	10.5
NFopt	Optimum Noise Figure Vds=3.0 V IDS=10 mA	12 GHz	dB		2.0
GA	Gain at Optimum Noise Figure Vds=3.0 V IDS=10 mA	12 GHz	dB		8.0
IDSS	Recommended IDSS Range for Optimum P1dB		mA		50- 86

DEVICE EQUIVALENT CIRCUIT	PARAMETER		VALUE
	Source Resistance	Rs	2.6	W
	Source Inductance	Ls	0.025	nH
	Drain-Source Resistance	Rds	230	W
	Drain-Source Capacitance	Cds	0.07	pF
	Drain Resistance	Rd	3.67	W
	Drain Pad Capacitance	Cpd	0.027	pF
	Drain Inductance	Ld	0.159	nH
	Gate Bond Wire Inductance	Lg	0.089	nH
	Gate Pad Capacitance	Cpg	0.05	pF
	Gate Resistance	Rg	0.2	W
	Gate-Source Capacitance	Cgs	0.314	pF
	Channel Resistance	Ri	6.9	W
	Gate-Drain Capacitance	Cgd	0.03	pF
	Transconductance	gm	55	mS
	Transit Time	tau	3.02	psec

ORDERING INFORMATION:

Chip	MwT-LP7	NOTE:
Package 70	MwT-LP770	For package information, please see supplementary application note in PDF format by clicking here. When placing your order or requesting a quotation, please specify Idss BIN range, wafer number if known, screening method, and visual level required.
Package 73	MwT-LP773


Standard Wafer Evaluation	Visual Level 1	Visual Level 3

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